Methods and apparatus for compiling instructions for a data processor

ABSTRACT

Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach comprises canonicalizing the “regular” 32-bit instruction addressing modes, and the second for the “compressed” 16-bit instruction addressing modes. In another aspect, a plurality of functions (up to and including all available functions) are called indirectly to allow addresses to be placed in a constant pool. Improved methods for instruction selection, register allocation and spilling, and instruction compression are provided. An improved SoC integrated circuit device having an optimized 32-bit/16-bit processor core implementing at least one of the foregoing improvements is also disclosed.

This application claims priority benefit of U.S. provisional patent application Ser. No. 60/343,730 filed Dec. 26, 2001 and entitled “Methods and Apparatus for Compiling Instructions for a Data Processor” which is incorporated herein by reference in its entirety.

COPYRIGHT

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of data processors, and specifically to methods and apparatus for compiling computer programs into machine-readable form.

2. Description of Related Technology

As is well known in the computer programming arts, a compiler is an entity which complies or translates high level programming languages (such as C, C++, etc.) into a assembly language or machine readable form for use by a digital processor. A variety of different configurations of and approaches to digital processor code compilers in general are known in the prior art. A treatise on the early development of compilers and other language processing systems is contained in “The History of Language Processor Technology in IBM,” by F. E. Allen in the IBM Journal of Research and Development, Vol. 25, No. 5, September 1981, pages 535-548.

Compiler Approaches Generally

Exemplary prior art compiler approaches are now described.

U.S. Pat. No. 6,367,071 to Cao, et al. issued Apr. 2, 2002 entitled “Compiler optimization techniques for exploiting a zero overhead loop mechanism” discloses a compiler loop optimization techniques to take advantage of a zero overhead loop mechanism (ZOLM) in a processor, e.g., a ZOLM in the form of a zero overhead loop buffer (ZOLB). A compiler generates a first set of code, and then applies optimizations to the first set of code so as to generate a second set of code configured to operate efficiently with the ZOLB. The optimizations are designed to increase the number of loops of the first set of code that can be accommodated in the ZOLB, to further reduce the overhead of the loops placed in the ZOLB, and to eliminate redundant loading of the ZOLB. Optimizations for increasing the number of loops that can be accommodated in the ZOLB include, e.g., conditional instructions, loop splitting and function inlining. Optimizations for further reductions in loop overhead include, e.g., loop collapsing and loop interchange. Data flow analysis and loop peeling is disclosed to avoid redundant loading of the ZOLB.

U.S. Pat. No. 6,308,323 to Douniwa issued Oct. 23, 2001 entitled “Apparatus and method for compiling a plurality of instruction sets for a processor and a media for recording the compiling method” discloses compiling a source program for a processor having a plurality of different instruction sets at high speed by selecting an optimum instruction set. The compiling method comprises dividing a source program into a plurality of modules according to a predetermined unit, compiling the respective modules with respective ones of the plurality of different instruction sets, providing data for evaluating an efficient compiling process based upon the module compilations with the respective instruction sets, selecting an optimum instruction set among the plurality of different instruction sets by comparing the evaluation data, and inserting an instruction set changing command at a necessary portion for changing the instruction set.

U.S. Pat. No. 6,305,013 to Miyamoto issued Oct. 16, 2001 entitled “Compiling method for generating target program in accordance with target processor type, compiling device, recording medium with compiling program recorded therein and recording medium with conversion table used in compiling recorded therein” discloses a compiling method of generating a code of a target program operable in a desired target processor, in which an amount of operations required for the code generation is reduced. Specifically, a code generating section comprises a first converting section and a second converting section. The first converting section refers to a first conversion table stored in a first storage device to generate a low-level code from a high-level code, while the second converting section refers to a second conversion table stored in a second storage device to generate an output code from the low-level code. In the second conversion table, output codes indicating the same or similar function are associated to the common low-level code.

U.S. Pat. No. 6,260,189 to Batten, et al. issued Jul. 10, 2001 entitled “Compiler-controlled dynamic instruction dispatch in pipelined processors” discloses techniques for improving the performance of pipelined processors by eliminating unnecessary stalling of instructions. In an illustrative embodiment, a compiler is used to identify pipeline dependencies in a given set of instructions. The compiler then groups the set of instructions into a code block having a field which indicates the types of pipeline dependencies, if any, in the set of instructions. The field may indicate the types of pipeline dependencies by specifying which of a predetermined set of hazards arise in the plurality of instructions when executed on a given pipelined processor. For example, the field may indicate whether the code block includes any Read After Write (RAW) hazards, Write After Write (WAW) hazards or Write After Read (WAR) hazards. The code block may include one or more dynamic scheduling instructions, with each of the dynamic scheduling instructions including a set of instructions for execution in a multi-issue processor.

U.S. Pat. No. 5,946,492 to Bates issued Aug. 31, 1999 entitled “Compiler that reduces call stack size through identification of stackless variables” discloses an optimizing compiler to identify what are referred to herein as stackless variables. A variable is said to be stackless for a given call statement if the calling program does not have a need for the information stored in the variable when the calling program resumes execution after the program that is the subject of the call statement returns control of the processor to the calling program. The decision of whether a variable is stackless or not for a given call statement is made by determining whether the live range of the particular variable spans the location of the call statement in question. If a variable's live range is found to cross the location of the call statement, it is not considered stackless. However, if a variable's live range is not found to cross the location of the call statement, it is considered to be stackless for that particular call statement

U.S. Pat. No. 5,850,551 to Takayama, et al. issued Dec. 15, 1998 entitled “Compiler and processor for processing loops at high speed” discloses a compiler comprising a loop detecting unit for extracting information of loops, and a high-speed loop applying unit generating a first loop exclusive instruction, placing the instruction immediately before the entry of a loop, generating second loop exclusive instructions, and placing the instruction at each place to branch to the entry of the loop. Application in the context of variable length instructions is also disclosed.

U.S. Pat. No. 5,845,127 to Isozaki issued Dec. 1, 1998 entitled “Language processor and language processing method to generate object programs by compiling source programs” discloses a language processor for source program compiling and object file generation having a function call counter section to count the number of calls for each function during syntax analysis, a function data storage section to store the call count for each function counted by the function call counter section and the code size of each code for each function generated according to the source program analysis results, and a specific space function designation section which refers to the call count and the code size for each function stored in said function data storage section and designates the functions to be placed in the specific area held by the microcomputer in the program space so that the total sum of the function code sizes does not become larger than the size of the specific area with placing priority to the functions with many calls.

U.S. Pat. No. 5,828,884 to Lee, et al. issued Oct. 27, 1998 entitled “Method for compiling a software program and executing on a system which converts data between different endian formats” discloses a method for compiling a software program and executing the program on a data processing system which performs conversion between data formatted in differing endian formats, namely big-endian and little-endian formats, also known as byte swapping. The disclosed compiler generates object offsets to data elements in a source code module, then adds a format base to the object offset to calculate a data aperture offset for each data element, which is then stored in an object code module. The format bases for the data elements are chosen according to the data type of the data element. A base memory address is bound to each data element at runtime, load-time or compile time. The base memory address for each data element is added to the data aperture offset for the data element to calculate a data aperture address for the data element. As the processor executes the program and performs a transfer of a data element between the processor and data storage device, the processor provides the data aperture address of the data element to the byte swapping device. The byte swapping device selectively byte swaps the data element during the transfer according to a relationship between the data aperture address and the data conversion apertures. The compiler generates data conversion aperture values and the processor programs the data conversion aperture values into aperture storage elements in the byte swapping device when loading the program into system memory for execution. The data conversion apertures are chosen based upon the set of data types comprised by the data elements, namely data types which require byte swapping and data types which do not.

U.S. Pat. No. 5,790,877 to Nishiyama, et al. issued Aug. 4, 1998 entitled “Method for controlling a processor for power-saving in a computer for executing a program, compiler medium and processor system” discloses in a processor system including a plurality of hardware resources, a method for arranging a program to suppress the power consumption by the resources includes the steps of determining which ones of the hardware resources are to be operated and from which instruction cycle to which instruction cycle to execute each instruction of the program; and based on the determination, adding an instruction to lower frequencies of clock signals inputted to the hardware resources and an instruction to restore the frequency at positions adjacent to the beginning and the end of the period during which the hardware resources are not operated and compiling the program. The processor system decodes the compiled program and lowers the frequency of the clock signal inputted to the hardware resources in accordance with the frequency lowering instruction and the frequency restoring instruction detected in the decoding step. The clock signals sent to the hardware resources are stopped by the frequency lowering instruction to the resource of the hardware resources for which the clock frequency may be lowered to zero.

U.S. Pat. No. 5,790,854 to Spielman, et al. issued Aug. 4, 1998 entitled “Efficient stack utilization for compiling and executing nested if-else constructs in a vector data processing system” discloses a computer-implemented method is provided for compiling software code that performs nested conditional constructs in vector data processors. A vector bit stack is provided to record which processing elements were activated and which processing elements were deactivated during execution of a nested conditional construct. Subsequently, when an end of a first nested conditional construct is encountered, a state of the processing elements at a point in time in which the first nested conditional construct was initiated may be popped off of the vector bit stack and a second conditional construct or any other operation may be executed. Therefore, conditional constructs may be executed while ensuring the proper state of the processing elements. The compiler program effectively utilizes the vector bit stack to store prior states of each of the processing elements of the vector data processor such that the processing elements may be efficiently restored to a correct intermediate value.

U.S. Pat. No. 5,752,035 to Trimberger issued May 12, 1998 entitled “Method for compiling and executing programs for reprogrammable instruction set accelerator” discloses a microprocessor having a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a set of program instructions, to provide an on chip reprogrammable instruction set accelerator (RISA). Reprogrammable execution units may be made using field programmable gate array technology having configuration stores. Techniques for translating a computer program into executable code relying on the RISA involve providing a library of defined and programmed instructions, and compiling a program using the library to produce an executable version of the program using both defined and programmed instructions. The executable version can be optimized to conserve configuration resources for the programmable execution unit, or to optimize speed of execution. Thus, seldom used programmed instructions in the final object code can be replaced with segments of defined instructions to conserve configuration resources. Alternatively, specially prepared sets of programmed instructions can be used to compile programs. A variety of versions are formed using separate sets of programmed instructions and the best final version is selected. In addition, commonly used segments of instructions can be synthesized into a programmed instruction dynamically.

U.S. Pat. No. 5,555,417 to Odnert, et al. issued Sep. 10, 1996 entitled “Method and apparatus for compiling computer programs with interprocedural register allocation” discloses optimization techniques implemented by means of a program analyzer used in connection with a program compiler to optimize usage of limited register resources in a processor. The first optimization technique, called interprocedural global variable promotion allows the global variables of a program to be accessed in common registers across a plurality of procedures. Moreover, a single common register can be used for different global variables in distinct regions of a program call graph. This is realized by identifying subgraphs, of the program call graph, called webs, where the variable is used. The second optimization technique, called spill code motion, involves the identification of regions of the call graph, called clusters, that facilitate the movement of spill instructions to procedures which are executed relatively less often. This decreases the overhead of register saves and restores which must be executed for procedure calls.

U.S. Pat. No. 5,450,585 to Johnson issued Sep. 12, 1995 entitled “Compiler with delayed conditional branching” discloses an optimization method and apparatus adapted for use on a compiler for generating machine code optimized for a pipeline processor. A compute-compare-branch sequence in a loop is replaced with a compare-compute-branch sequence. A compute-compare-branch sequence is a sequence of instructions to compute the value of one or more variables, execute a comparison involving the variables, and execute a conditional branch conditioned on the comparison. In the compare-compute-branch sequence, the instructions of the compute-compare-branch sequence are reordered as follows. First, the comparison is executed. In the compare-compute-branch sequence, the comparison involves previously set values of the variables. Second, the computation is executed to compute the current values of the variables. Finally, the conditional branch conditioned on the latter comparison is executed so as to have the effect of executing during the previous execution of the sequence. One or more temporary variables store the previous values of the variables. They are set to the values of the variables at the end of the compare-compute-branch sequence. Before execution of the loop, the temporary variables are set so that the condition will not be met the first time the sequence executes. After execution of the loop, a comparison and a conditional branch are executed. The comparison involves the temporary variables, and the conditional branch is conditioned on the comparison.

U.S. Pat. No. 5,293,631 to Rau, et al. issued Mar. 8, 1994 entitled “Analysis and optimization of array variables in compiler for instruction level parallel processor” discloses a process for optimizing compiler intermediate representation (IR) code, and data structures for implementing the process. The process is embodied in a compiler computer program operating on an electronic computer or data processor with access to a memory storage means such as a random access memory and access to a program mass storage means. The compiler program reads an input source program stored in the program mass storage means and creates a dynamic single assignment intermediate representation of the source program in the memory using pseudo-machine instructions. To create the dynamic single assignment intermediate representation, during compilation, the compiler creates a plurality of virtual registers in the memory for storage of variables defined in the source program. Means are provided to ensure that the same virtual register is never assigned to more than once on any dynamic execution path. An expanded virtual register (EVR) data structure is provided comprising an infinite, linearly ordered set of virtual register elements with a remap function defined upon the EVR. Calling the remap function with an EVR parameter causes an EVR element which was accessible as [n] prior to the remap operation to be accessible as [n+1] after the remap operation. A subscripted reference map comprising a dynamic plurality of map tuples is used. Each map tuple associates the real memory location accessible under a textual name with an EVR element. A compiler can use the map tuple to substitute EVR elements for textual names, eliminating unnecessary load operations from the output intermediate representation.

U.S. Pat. No. 5,287,510 to Hall, et al. issued Feb. 15, 1994 entitled “Method for improving the efficiency of arithmetic code generation in an optimizing compiler using machine independent update instruction generation” discloses a process within an optimizing compiler for transforming code to take advantage of update instructions available on some computer architectures. On architectures which implement some form of autoindexing instructions or addressing modes, this process is intended to improve the code generated for looping constructs which manipulate arrays in memory. The process comprises selecting memory referencing instructions inside loops for conversion to update forms, modifying those instructions to an update form available on a particular processor, and applying an offset compensation to other memory referencing instructions in the loop so as to enable the program to still address the appropriate locations while using the available autoindexing instructions. The improved compiler and compiler process enables the compiler to convert those program instructions that would otherwise convert to autoindexing instructions not supported by the processor to autoindexing instructions that are supported.

U.S. Pat. No. 5,274,818 to Vasilevsky, et al. issued Dec. 28, 1993 entitled “System and method for compiling a fine-grained array based source program onto a course-grained hardware” discloses a parallel vector machine model for building a compiler that exploits three different levels of parallelism found in a variety of parallel processing machines, and in particular, the Connection Machine™ Computer CM-2 system. The fundamental idea behind the parallel vector machine model is to have a target machine that has a collection of thousands of vector processors each with its own interface to memory. Thus allowing a fine-grained array-based source program to be mapped onto a course-grained hardware made up of the vector processors. In the parallel vector machine model used by CM Fortran 1.0, the FPUs, their registers, and the memory hiearchy are directly exposed to the compiler. Thus, the CM-2 target machine is not 64K simple bit-serial processors. Rather, the target is a machine containing 2K PEs (processing elements), where each PE is both superpipelined and superscalar. The compiler uses data distribution to spread the problem out among the 2K processors. A new compiler phase is used to separate the code that runs on the two types of processors in the CM-2; the parallel PEs, which execute a new RISC-like instruction set called PEAC, and the scalar front end processor, which executes SPARC or VAX assembler code. The pipelines in PEs are filled by using vector processing techniques along the PEAC instruction set. A scheduler overlaps the execution of a number of RISC operations.

U.S. Pat. No. 5,247,668 to Smith, et al. issued Sep. 21, 1993 entitled “Methods of realizing digital signal processors using a programmed compiler” discloses a compiler for a digital signal processor allowing the designer to specify separately function, accuracy and throughput. The compiler employs a word structure having the signal attributes of bits, digits and subwords which all have a direct relationship to the size of the processor and throughput. From a budget of working bits and clock cycles implicit in the specification of accuracy and throughput the compiler is able to choose the optimal word structure for the application. The compiler can also propagate throughout an icon network, used for the specification of function, various estimation attributes such as word growth and quantization noise, which allow the designer to observe the effect of design changes without recourse to simulation.

U.S. Pat. No. 5,088,034 to Ihara, et al. issued Feb. 11, 1992 entitled “Compiling method for determining programs to be executed parallelly by respective processors in a parallel computer which transfer data with a data identifier to other processors” discloses a compiler for generating from a serially processed type source program described in a high level language the object codes to be executed in parallel by a parallel processor system which is composed of a plurality of processors marked with respective identification numbers and in which inter-processor data transfer system for identifying data for transfer by data identifiers is adopted. The serially executed source program is first translated to programs to be executed in parallel. The inter-processor data transfer processing is extracted from the flow of processings involved in executing the programs for parallel execution resulting from the above-mentioned translation, and all the interprocessor data transfer processings are attached with data identifiers such that no overlap takes place.

U.S. Pat. No. 4,965,724 to Utsumi, et al. issued Oct. 23, 1990 entitled “Compiler system using reordering of microoperations to eliminate interlocked instructions for pipelined processing of assembler source program” discloses compiling a source program described with assembler instructions, each of which defines microoperations, into a target program for use in a digital signal processor. If two of the assembler instructions are interlocked with each other and if another assembler instructions which is not associated with the interlocked instructions is present, it is inserted between the interlocked instructions to thereby reorder the microoperations of the source program. Thereafter, the microoperations thus reordered are combined so as not to conflict with each other with regard to the fields of the assembler instructions and resources used by the assembler instructions. Prior to combining the microoperations, whether or not a basic block of assembler instructions included in the source program having a loop may be determined. If so, a head portion of the basic block forming the loop may then be transferred to a tail portion of the basic block forming the loop.

U.S. Pat. No. 4,827,427 to Hyduke issued May 2, 1989 entitled “Instantaneous incremental compiler for producing logic circuit designs” discloses a computer aided logic design system for instantaneously compiling circuit component entries into a schematic model which provides immediate simulation of each entry or deletion into the electronic circuit schematic. The system includes software for processing logic designs which produces a signal table for storing all inputs and outputs of chips stored in a specification table. The processor also produces a call table that lists all chips from the chips specification table from which chip models can be retrieved and executed. Additionally, a software routine produces a netlist transfer table that specifies the transfer of signals within the signal table produced by software processing, which correspond to the signal distribution in the circuit being designed. After production of the signal table, specification table, call table and netlist transfer table, a software processing routine executes sequential values retrieved from the call table and netlist transfer table to create a second signal table which is compared with the first signal table. The software processing routine continuous to execute values retrieved from the call table and netlist transfer table and compare the first and second signal tables until both the second signal table being created is identical with the first signal table stored in memory. The software processing means also includes a delay which delays sequential processing until the comparing step for comparing the second signal table with the first signal table reaches a stable state.

Constants and Constant Pools

Constant values are used in all kinds of programs and many programming languages. Since a constant is read-only and may be used many times in a program, constants may be optimized to, inter alia, eliminate any duplicates. The well known “constant pool” is a set of data structures containing data that remains fixed throughout the execution of a program unit. By pooling, or putting all constants together in the same locations, the size of a program can be greatly reduced. This helps eliminate wasted space. In a low level language, a programmer might maintain a constant pool by hand. In a high level language, programming tools are used to maintain a constant pool.

Using a mechanism such as an ID (an index into the constant pool), a program can copy a constant value from the constant pool. When a new value is added to a constant pool, it is given a unique ID.

Constant pools may contain, among other things: string constants, information for exception handlers, data type descriptors for various data types, and function call descriptors (metadata describing a called function). For example, a constant pool for a program that prints text, named PrintText, may contain a function descriptor describing an invocation of the function ‘print’. The function descriptors are then followed by a set of constant strings, which represent the text to print.

Various approaches to structuring and accessing constants in RISC processors have been suggested. For example, U.S. Pat. No. 6,282,633 to Killian, et al. (Tensilica) issued Aug. 28, 2001 and entitled “High data density RISC processor” discloses a RISC processor implementing an instruction set which seeks to optimize the relationship between the number of instructions required for execution of a program, clock period and average number of clocks per instruction, as well as the equation S=IS*BI, where S is the size of program instructions in bits, IS is the static number of instructions required to represent the program (not the number required by an execution) and BI is the average number of bits per instruction. This processor is intended to lower both BI and IS with minimal increases in clock period and average number of clocks per instruction. The processor implements a variable-length encoding.

In attempts to lower IS and IE (the number of instructions required to implement a given algorithm), the Tensilica invention uses single instructions that combine that functions of multiple instructions typically found in RISC and other instruction sets. An example of a simple compound instruction is left shift and add/subtract. The Tensilica approach also utilizes a load instruction to reference constants, thereby ostensibly providing lower IS and IE than using a sequence of instructions if the load itself requires only a single instruction. Compilers compatible with processors offered by MIPS Technologies, for example, dedicate one of the 31 general registers to hold a pointer to a constant pool where 4-byte and 8-byte floating point constants are stored. If the area addressed by this register is less than a predetermined size (e.g., 64 KB offset range in loads for MIPS), the constants may be referenced by a single load instruction. For a constant that is referenced once, the 32-bit load instruction plus the 32-bit constant is the same total size as two instruction words. If the constant is referenced twice or more, the constant pool provides smaller total size. The tradeoff is different for other instruction lengths, such as the 24-bit size of the Tensilica approach, where the constant pool plus load is 56 bits vs. 48 bits for a pair of 24-bit instructions.

U.S. Pat. No. 6,275,830 to Muthukkaruppan, et al. issued Aug. 14, 2001 and entitled “Compile time variable size paging of constant pools” discloses a method and apparatus for paging data in a computer system. A set of data associated with a program unit is divided into pages such that no item of the set of data spans more than one page. The size of one page may vary from the size of another. When the program unit is compiled, metadata is generated that indicates the division of items into pages. At load time, a page mapping is generated based on the metadata. The page mapping is used to locate an item that belongs to the set of data. Other parts of the program unit, such as byte code, can contain references to items in the constant pool. Each reference specifies the number of the page in which the corresponding item will be stored at runtime, and the offset of that item within the page.

“Coloring” and Register Spilling

So-called “optimizing” compilers utilize one or more optimization algorithms such as common sub-expression elimination, moving code out of loops, eliminating dead code, strength reduction, and register assignment to make the code more compact and efficient. Register assignment can be very significant, since operations wherein the operands are obtained from and results return to registers can proceed at a much higher speed than those which require memory or storage device access.

The article “An Overview of the PL.8 Compiler,” by Auslander and Hopkins appearing in the ACM SIGPLAN Notices, Vol. 17, No. 6, June 1982, pages 22-31 describes an optimizing compiler with register assignment. Similarly, “Measurement of Code Improvement Algorithms,” in “Information Processing′80,” J. Cocke and P. W. Markstein, (edited by S. H. Lavington), pages 221-228, North-Holland, Amsterdam, (1980), and “A Program Data Flow Analysis Procedure,” F. E. Allen and J. Cocke, Communications ACM 19, pages 137-147 (1976), both discuss the objectives and concepts involved in the design of optimizing compilers.

U.S. Pat. No. 5,659,754 to Grove, et al. issued Aug. 19, 1997 and entitled “Method and apparatus for an improved optimizing compiler” discloses an optimizing compiler process and apparatus for more accurately and efficiently identifying live variable sets in a portion of a target computer program, so as to more efficiently allocate registers in a computer central processing unit. The process of the invention includes the steps of performing a static single assignment transform to a computer program, including the addition of phi functions to a control flow graph. Basic blocks representing a use of a variable are further added to the control flow graph between the phi functions and definitions of the variables converging at the phi functions. A backward dataflow analysis is then performed to identify the live variable sets. The variables in the argument of phi functions are not included as a use of those variables in this dataflow analysis. The dataflow analysis may be iteratively performed until the live variable sets remain constant between iterations.

Many compilers assume a large number of registers during their optimization procedures. In fact the result of each different computation in the program is conventionally assigned a different register. At this point a register allocation procedure is invoked to assign real registers, from those available in the machine, to these different (symbolic) registers. Conventional approaches use a subset of the real registers for special purposes while the remaining set is assigned locally. Between these assignments, results which are to be preserved are temporarily stored, and variables are redundantly reloaded. These approaches are inefficient in that significant processor cycles are wasted while data is being transferred between storage and registers or conversely, data is accessed from and returned to storage directly bypassing the registers completely.

“Register Allocation Via Coloring,” by G. J. Chaitin et al, appearing in Computer Languages, Vol. 6, pages 47-57, Pergamon Press, Great Britain, 1981, referred to above, describes the basic concepts of register allocation via coloring but utilizes a different approach to the “spilling” problem.

“The 801 Minicomputer,” by George Radin, published in the ACM SIGPLAN Notices, Vol. 17, No. 4, April 1982, pages 39-47, is an overview of an experimental minicomputer which incorporated an optimizing compiler utilizing the concepts of register allocation via coloring described in the above-referenced article by Chaitin.

The foregoing references observed that the register assignment or allocation problem is equivalent to the graph coloring problem, where each symbolic register is a node and the real registers are different colors. When two symbolic registers have the property that there is at least one point in the program when both their values must be retained, that property is modeled on the graph as a vertex or edge between the two nodes. Thus the register allocation problem is analogous to coloring the graph so that no two nodes connected by a vertex are colored the same. This in effect says that each of these two (or more) nodes must be stored in different registers.

However, a potentially significant shortcoming of the register allocation via coloring procedure referenced above regards the “spilling” problem; i.e., the situation where there are more data items to be retained than there are machine registers available. A number of different solutions for the spilling problem have been proffered, the following being exemplary.

U.S. Pat. No. 4,571,678 to Chaitin issued Feb. 18, 1986 and entitled “Register allocation and spilling via graph coloring” discloses an optimizing compiler which receives a high level source language program and produces machine interpretable instructions, including a method for assigning computational data utilized by the program to a limited number of high speed machine registers in a target CPU. Specifically, the patent discloses methods for determining that there are not enough registers available in the CPU to store all of the data required at the given point in time and for the determining which data should be stored in the system memory until they are actually needed. These methods utilize a graph reduction and coloring approach in making the “spill” decisions.

U.S. Pat. No. 5,249,295 to Briggs, et al. issued Sep. 28, 1993 entitled “Digital computer register allocation and code spilling using interference graph coloring” discloses a method for allocating internal machine registers in a digital computer for use in storing values defined and referenced by a computer program. An allocator in accordance with the present invention constructs an interference graph having a node therein for the live range of each value defined by a computer program, and having an edge between every two nodes whose associated live ranges interfere with each other. The allocator models the register allocation process as a graph-coloring problem, such that for a computer having R registers, the allocator of the present invention iteratively attempts to R-color the interference graph. The interference graph is colored to the extent possible on each iteration before a determination is made that one or more live ranges must be spilled. After spill code has been added to the program to transform spilled live ranges into multiple smaller live ranges, the allocator constructs a new interference graph and the process is repeated.

U.S. Pat. No. 5,946,491 to Aizikowitz, et al. issued Aug. 31, 1999 entitled “Register allocation method and apparatus for generating spill code as a function of register pressure compared to dual thresholds” discloses a method and apparatus for minimizing spill code in regions of low register “pressure.” The invention determines the register pressure at various locations in the computer program. When a live range is selected for spilling, spill code is generated to relieve the register pressure in regions of high register pressure, while spill code is avoided in regions of low register pressure. In this manner a minimum amount of spill code is generated, enhancing both the compile time and the run time of the resultant instruction stream.

U.S. Pat. No. 6,090,156 to MacLeod issued Jul. 18, 2000 and entitled “System for local context spilling for graph coloring register allocators” discloses a register allocator for allocating machine registers' during compilation of a computer program. The register allocator performs the steps of building an interference graph, reducing the graph using graph coloring techniques, attempting to assign colors (i.e. allocate machine registers to symbolic registers), and generating spill code. The spill code is generated by a local context spiller which processes a basic block on an instruction by instruction basis. The local context spiller attempts to allocate a machine register which is free in the basic block. If the basic block does not have any free machine registers, the local context spiller looks ahead to select a machine register for spilling. The register allocator improves the performance of a compiler by limiting the rebuilding of the interference graph and the number of the graph reduction operations.

However, despite the broad array of prior art compiler and optimization techniques, the prior art lacks the ability to effectively and efficiently handle variable- or mixed-length instruction formats within the instruction stream, including dynamically determining which form (of several possible) of a given instruction that it must generate, and optimising the selection of such varying formats based on one or more parameters. Furthermore, prior art techniques of register allocation and spilling handling are not optimized for the aforementioned mixed-length ISA environment, and do not take into account register set usage based on the ISA. For many of the smaller instructions, there are limitations to a subset of the general purpose registers. For example, of the “normal” number (e.g., 32) of registers, only a subset (e.g., 8) are available for the smaller or compressed instructions. Although these registers are the same color as the normal registers, there is no current technique in assigning a priority to the subset of the registers. Prior art coloring algorithms, including those of Chatin, et al described above, do not consider the actual register being selected. These algorithms are only concerned with edges and interference, and have no heuristic for choosing one machine register over another in the general purpose case (outside of the case where a register is assigned specifically to a GPR of a certain color by other optimizations).

Chatin and others do address the concept of a register that can have different colors: it is up to the coloring algorithm to determine which color to select based on register pressure and contention. There is no effort to select a specific color based on further compressing the size of the instruction, or reducing the overall size of the compiled function.

Spilling in general is assumed to be to memory locations since there are not enough GPRs to accommodate all of the virtual registers being used by the optimising compiler. This is the fundamental definition—to spill means to use memory to temporarily hold the results of an instruction due to too many registers alive across the span of the specific instruction. The prior art is generally deficient at localizing such spilling.

Address Canonicalization

Another area of interest in compiler and instruction set optimization relates to address canonicalization; see, e.g., the “canonical reduction sequence” on pg. 152 of “Principles of Compiler Design” by Aho and Ullman, April 1979. In practice, addresses are canonicalized to the specifics of the machine for which code is being generated. Typical decisions are made to base/index/scale operations as well as size of displacements and allowed formats (for example, a load instruction may have a base register plus either an immediate offset or an index register with a scaling factor). By generating the same sequence of instructions for the address (no matter how redundant), one hopes to take advantage of global common sub-expression elimination, such as that defined in “Global Optimization by Suppression of Partial Redundancies” by Morel and Renvoise, CACM February 1979; “The Pascal XT Code Generator” by Drechsler and Stadel, SIGPLAN Notices, August 1987; and Cliff Click, “Global code motion/global value numbering”, ACM SIGPLAN Notices, v.30 n.6, p. 246-257, June 1995.

One significant problem associated with prior art canonicalization techniques is that the decisions as to how to canonicalize the necessary address must be performed prior to the common sub-expression elimination (unless these very costly algorithms are run more then once, which is not practical in practice). Hence, an improved method for choosing the correct address canonicalization when an instruction set has 2 or more distinct sets of addressing is needed.

SUMMARY OF THE INVENTION

The present invention satisfies the aforementioned needs by an improved method and apparatus for compiling instructions in the context of a variable- or mixed-length digital processor ISA.

In a first aspect of the invention, an improved method of compiling an instruction set for a digital processor having variable length instructions is disclosed. The method generally comprises: generating at least one instruction; canonicalizing the address calculation associated with the at least one instruction in at least first and second instances, the first instance relating to a first instruction length, and the second instance relating to a second instruction length being smaller than the first length; and selecting one of the first or second instances based on producing the smallest instruction set. In one exemplary embodiment, the digital processor comprises an extensible RISC processor having a mixed freeform 16- and 32-bit ISA.

In a second aspect of the invention, an improved digital processor is disclosed. The processor comprises an instruction set being generated using the method comprising: performing address calculations associated with a plurality of instructions in said set in a plurality of forms, said plurality comprising at least a first form for first addressing modes, and a second form for second addressing modes; determining which of the first or second forms will optimize the instruction set; selecting the first or second form based at least in part on the act of determining; and compiling the instruction set based at least in part on the act of selecting.

In a third aspect of the invention, an improved method of streamlining call functions within a digital processor is disclosed, generally comprising: indirectly calling a plurality of functions; and placing the addresses associated with the plurality of functions in at least one constant pool; wherein the act of indirectly calling comprises using a reduced-length instruction format. In one exemplary embodiment, the reduced-length format comprises a 16-bit format used in a variable length ISA.

In a fourth aspect of the invention, an improved method for instruction selection is disclosed. In one exemplary embodiment, the methodology comprises first reading all or a subset of the instructions under consideration, then translating each selected instruction and verifying that the translation is complete and valid. Once these steps have been completed, the translated instructions are examined to determine which is smaller. The “best” version of the instruction(s) is selected based on one or more selection criteria.

In a fifth aspect of the invention, an improved method of reducing instruction pairs down to a lesser number of operations is disclosed. In one exemplary embodiment, compare/branch instruction pairs are compressed to a lower number of instructions.

In a sixth aspect of the invention, an improved method of register allocation is disclosed. In one exemplary embodiment, the method comprises: attempting to “color” a graph with a predetermined number n of registers; if spilling is required (e.g., more than n−1 registers alive in any one basic block), then reassigning the chosen registers to the remaining general purpose registers (GPRs), and inserting copies into the graph between these two “banks” (colors) of registers. After spilling has occurred, the methodology utilizes coalescing of instructions (i.e., the elimination of registers alive across an instruction) to “clean up” the spills. The disclosed methodology further improves the locality of spilling in effect by utilizing less “efficient” registers of another color.

In a seventh aspect of the invention, an improved integrated circuit (IC) device generated using one or more of the foregoing methodologies is disclosed. In one exemplary embodiment, the device comprises an extensible RISC processor having a multi-stage pipeline (e.g., comprising instruction fetch, decode, execute, and writeback stages) embodied in an SoC device. The device also included on-chip embedded memory and peripheral functions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is logical flow diagram illustrating one exemplary embodiment of address calculation according to the present invention.

FIG. 1 a is a logical flow diagram illustrating one exemplary embodiment of address selection in the method of FIG. 1.

FIG. 2 is logical flow diagram illustrating one exemplary embodiment of the call reduction methodology according to the present invention.

FIG. 3 is logical flow diagram illustrating generally the methodology of instruction selection of the present invention.

FIG. 4 is a logical flow diagram illustrating one exemplary embodiment of the methodology for constant pool plus instruction size selection (PC-relative loads) according to the present invention.

FIG. 5 is a logical flow diagram illustrating one exemplary embodiment of the compare-branch pair reduction methodology of the present invention.

FIG. 6 is logical flow diagram illustrating one exemplary embodiment of register allocation methodology of the present invention.

FIG. 7 is block diagram illustrating an exemplary embodiment of an SoC integrated circuit device incorporating using the improved address calculation and other aspects of the ISA of the invention.

DETAILED DESCRIPTION

Reference is now made to the drawings wherein like numerals refer to like parts throughout.

As used herein, the term “processor” is meant to include any integrated circuit or other electronic device (or collection of devices) capable of performing an operation on at least one instruction word including, without limitation, reduced instruction set core (RISC) processors such as for example the ARCtangent™ user-configurable core produced by the Assignee hereof, central processing units (CPUs), and digital signal processors (DSPs). The hardware of such devices may be integrated onto a single substrate (e.g., silicon “die”), or distributed among two or more substrates. Furthermore, various functional aspects of the processor may be implemented solely as software or firmware associated with the processor.

Additionally, it will be recognized by those of ordinary skill in the art that the term “stage” as used herein refers to various successive stages within a pipelined processor; i.e., stage 1 refers to the first pipelined stage, stage 2 to the second pipelined stage, and so forth.

Such stages may comprise, for example, instruction fetch, decode, execution, and writeback stages.

As used herein, the term “extension” is meant to broadly refer to any instruction, hardware, or other device which does not exclusively form part of the “base case” core instruction set or architecture, and is in no way limited to the specific instructions or hardware explicitly described herein.

As used herein, the term “canonical”, “canonicalize” and “canonicalization” refer generally to the process whereby code is converted to a standard form or syntax, and/or redundancies removed such as through common sub-expression elimination and other techniques.

Lastly, any references to hardware description language (HDL) or VHSIC HDL (VHDL) contained herein are also meant to include other hardware description languages such as Verilogg. Furthermore, an exemplary Synopsys® synthesis engine such as the Design Compiler 2000.05 (DC00) may be used to synthesize the various embodiments set forth herein, or alternatively other synthesis engines such as Buildgates® available from, inter alia, Cadence Design Systems, Inc., may be used. IEEE std. 1076.3-1997, IEEE Standard VHDL Synthesis Packages, describes an industry-accepted language for specifying a Hardware Definition Language-based design and the synthesis capabilities that may be expected to be available to one of ordinary skill in the art.

It will be appreciated that while the following discussion is cast in terms of the ARCompact ISA and ARCtangent processor produced by the Assignee hereof, the present invention may be readily applied to other suitable types of digital processors and architectures as referenced above by those of ordinary skill in the art given the present disclosure and its Appendices.

The ARCtangent-A5 processor is a 32-bit four stage pipeline RISC architecture that implements the ARCompact™ instruction set. The ARCompact ISA is described in detail in co-owned, co-pending U.S. provisional patent application No. 60/353,647 filed Jan. 31, 2002 and entitled “Configurable Data Processor With Multi-Length Instruction Set Architecture” which is incorporated herein by reference in its entirety. ARCompact™ is an instruction set architecture (ISA) that allows designers to mix 16 and 32-bit instructions on its 32-bit user-configurable processor. The key benefit of the ISA is the ability to cut memory requirements on a SoC (system-on-chip) by significant percentages, resulting in lower power consumption and lower cost devices in deeply embedded applications such as wireless communications and high volume consumer electronics products.

The main features of the ARCompact ISA include 32-bit instructions aimed at providing better code density, a set of 16-bit instructions for the most commonly used operations, and freeform mixing of 16- and 32-bit instructions without a mode switch—significant because it reduces the complexity of compiler usage compared to competing mode-switching architectures. The ARCompact instruction set expands the number of custom extension instructions that users can add to the base-case ARCtangent™ processor instruction set. The ARCtangent processor architecture allows users to add as many as 69 new instructions to speed up critical routines and algorithms. With the ARCompact ISA, users can add as many as 256 new instructions. Users can also add new core registers, auxiliary registers, and condition codes. The ARCompact ISA thus maintains and expands the user-customizable features of ARC's configurable processor technology.

As 32-bit architectures become more widely used in deeply embedded systems, code density can have a direct impact on system cost. Typically, a very high percentage of the silicon area of a system-on-chip (SoC) is taken up by memory.

The ARCompact ISA delivers high density code helping to significantly reduce the memory required for the embedded application, an important factor for high-volume consumer applications, such as flash memory cards. In addition, by fitting code into a smaller memory area, the processor potentially has to make fewer memory accesses. This can cut power consumption and extend battery life for portable devices such as MP3 players, digital cameras and wireless handsets. Additionally, the new, shorter instructions can improve system throughput by executing in a single clock cycle some operations previously requiring two or more instructions. This can boost application performance without having to run the processor at higher clock frequencies.

The support for freeform use of 16- and 32-bit instructions advantageously allows compilers and programmers to use the most suitable instructions for a given task, without any need for specific code partitioning or system mode management. Direct replacement of 32-bit instructions with new 16-bit instructions provides an immediate code density benefit, which can be realized at an individual instruction level throughout the application. As the compiler is not required to restructure the code, greater scope for optimizations is provided, over a larger range of instructions. Application debugging is also more intuitive because the newly generated code follows the structure of the original source code.

Since the foregoing exemplary ARCompact ISA (as well as other ISAs) allows for variable length instructions within the instruction stream, the compiler employed for such applications must utilize significant complexity of analysis to determine which form of the instruction that it must generate. There are several components to this analysis, now described in detail.

Address Calculation and Selection—Typically, when a compiler generates an instruction that uses some sort of memory address, it creates the effective address operand and canonicalizes this operand in such a way that global optimizations can be done on the address components. This canonicalization takes into account displacement limitations, address forms (can there be a base register and an index register for example), and other factors. So for a machine that only allows one base register with no index, scale, or offset, the compiler will typically generate something of the form:

MOV r0 <- <addr of var + nearest “page” offset of available disp> // a “page” is the known offset of the variable within the local data section // divided by the total range of the displacement. For example, a machine // that allows −32/31 would divide the offset by 64 and use that “page” // value in the above calculation. ADD r1 <- r0,<remainder of displacement that fits within available disp> MPY r2 <- r3,#4 scale index by element size ADD r4 <- r1,r2 address fully calculated now LOAD r5 <- [r4] In machines with large displacements, the foregoing is not prohibitive for code generation. Classic optimization phases of the type well known in the art can reduce the number of instructions by common sub-expression elimination and the like.

With the variable-length ISAs such as ARCompact, however, there are several issues to be considered since the compressed (e.g., 16-bit) instructions use such comparatively small offsets. Generating the above code to fit within +/−32 bytes would create an undesirable number of instructions, where alternatively one “regular” 32-bit instruction with its wide range of offsets could be used.

To solve this problem, the methodology 100 of the present invention (FIG. 1) canonicalizes the address calculation in a plurality different ways per step 104. In one exemplary embodiment, the aforementioned plurality comprises two; e.g., the address calculation is canonicalized first for the “regular” 32-bit instruction addressing modes, and second for the “compressed” 16-bit instruction addressing modes. It will be recognized, however, that the methodology 100 of the present invention is not restricted to two-length ISAs such as ARCompact, but rather may also be applied to ISAs with three or more differing instruction forms, as well as to ISAs with different addressing modes (e.g., section relative addressing vs. direct variable addressing, or small data section addressing vs. section relative addressing vs. direct variable addressing, etc.).

Hence, in the exemplary embodiment, the LOAD instruction of the above example would have two (2) effective address operands (EAs) as the sources to the load instruction.

Next, classic optimization phases such as common sub-expression elimination, moving code out of loops, eliminating dead code, strength reduction, induction variable elimination, and register assignment may be employed (step 106) to reduce the instructions further. For example, the following exemplary code illustrates how such optimization phases may be performed:

1) Common sub-expression elimination:-    ADD R100 <- R101,R102    ....    ADD R200 <- R102,R101 Would then be converted to:    ADD R100 <- R101,R102    ....    COPY R200 <- R100 2) Moving code out of loops -    for (int I = 10; I < n; I++) {     double a = sin(x);     b[I] = b[I] * a;     } would effectively be treated as:    double a = sin(x);    for (int I = 10; I < n; I++) {     b[I] = b[I] * a;     } 3) Eliminating dead code -    int a = x+2;    a = y/3; The first calculation of ‘x+2’ would be killed if no other use of it and the assignment into ‘a’ would be killed generally. 4) Strength reduction -    int x = y *2; // typically an expensive instruction operation    int x = y+y; // strength reduced into simpler and faster instruction. 5) Induction variable elimination -    for (int I = 0; I < n; I++) {     a[I] = b[I] * dx;     } can be optimized as follows:    int j = n;    int a1 = a,*b1 = b;    while (n−−) *a1++ = *b1++ dx; 6) Register assignment -    // the following two instructions can be combined    add r0,r13,r14    mov r15,r0    // into (as long as no use of r0)    add r15,r13,r14

It will be recognized that other optimizations may be optionally employed as well, the forgoing being merely illustrative.

The methodology 100 next requires determining which form of the addressing generated per step 104 will generate the fewest number of instructions (step 108). This form is subsequently selected for the instruction form per step δ 10. This approach allows the selective determination of which instruction addressing mode is desired, with the goal being that the fewest possible instructions will be generated (and the instruction size being optimized as well).

The selection process of step 110 comprises in one exemplary embodiment use of a Single Static Assignment (SSA) approach of the type generally well known in the programming arts; see FIG. 1 a. Specifically, the primary property of this approach is that all assignments are conducted to a unique register across the function body. Since every register has exactly one definition, “def-use” lists may be constructed while in the SSA form. These lists allow the programmer to see how many times the definition was used. Since several other optimization phases “common up” similar code, the address form which is most beneficial can be readily identified.

As a specific example of the foregoing, if the 32-bit canonicalized address was used only once per the def-use list, while the 16-bit address was used 10 times, the 16-bit form would be selected. In the case where the number of uses between the different forms is equal, the smaller (e.g., 16-bit) form is selected in order to compress code space.

Exemplary code used in accomplishing the foregoing in the context of the ARCompact processor is provided in Appendix I (canonicalization) and Appendix II (address selection) hereto.

Call Instruction Reduction—In another aspect of the invention, an improved methodology for streamlining call functions within the processor is disclosed (FIG. 2). Specifically, in the exemplary embodiment FIG. 2, a plurality of callable functions are first provided within the processor (step 202). Per step 204, a determination is made as to how many times a given function is called. In the illustrated embodiment, a minimum number n of calls (e.g., 3) is required in order to make use of the indirect call methodology beneficial. Per step 206, this minimum number n is compared to the number of calls determined per step 204; if greater than or equal to this number n, the indirect form is used (step 208). Per step 208, functions are called (step 210) using an indirect approach of the type well known in the programming arts. Using this indirect call approach, the addresses may be placed in the constant pool (step 212).

This methodology 200 advantageously allows the call instruction(s) to be selectively reduced to a 16-bit form. This methodology also does not create undue register pressure at register allocation time, since the indirect call can be easily reversed into a “normal” call instruction (albeit at a loss of code compression).

The ‘indirect_calls’ routine provided below is an example of code used to implement the foregoing functionality in the context of one function; it will be recognized that this methodology may be utilized for any number of different functions.

static int deal_with_indirect_calls(IL_entry *def,Register r) {  int cnt = 0,did_something = 0;  int scnt = il_src_cnt(def);  if (scnt > 1) return 0;  // don't know what this is  if (debug_ssa_tog) {   printf(“[ssa] R%d-def: ”,r); print_il(def);   }  for_each_ref_il(ref,r) {   IL_opcode op = il_op(ref);   if (Oneof2(op,il_CALL,il_XCALL)) {     IL_opd *f = &CALL_FUNC(ref);     if (f->type == REG_i && oREG(*f) == r) {      cnt++;      }     }   } end_for  if (cnt > 3) {   // call foo <-- 4 bytes   //   // ld   r1,[pc-rel zpool]   <-- 2 bytes + (4 for store)   //   // so for 3 calls: 8 bytes normally and 8 bytes for 16-bit.   // So this only benefits when called 3 or more times....   if (debug_ssa_tog) {     printf(“..no change: uses=%d\n”,cnt);     }   return 0;   }  for_each_ref_il(ref,r) {   IL_opcode op = il_op(ref);   if (Oneof2(op,il_CALL,il_XCALL)) {     IL_opd *f = &CALL_FUNC(ref);     if (f->type == REG_i && oREG(*f) == r) {      *f = SRC1(def);      if (debug_ssa_tog) {       printf(“..ref-change: ”); print_il(ref);       }      did_something = 1;      DEC_REF_COUNT(r);      }     }   } end_for  return did_something;  }

-   -   © 2000-2002 ARC International. All rights reserved.

As illustrated in the foregoing code example, the availability of the constant pool and the 16-bit pc-relative load instruction, plus the 16-bit jump-indirect instruction, further reduces the size of the resulting code as the number of occurrences calling the one function increases. In this particular instance, the trade-off in ld/jmp is beneficial when 3 or more occurrences of the function are found within the function.

Instruction Selection—Referring now to FIG. 3, another aspect of the present invention is described. As shown in the exemplary methodology of FIG. 3, the present invention generally determines instruction selection; i.e., which is more desirable between the various (e.g., 16-bit or 32-bit) instruction length options. Specifically, the methodology 300 comprises first reading all or a subset of the instructions under consideration (step 302), then translating each selected instruction (step 304) and verifying that the translation is complete and valid (step 306). Once these steps have been completed, the translated instructions are examined to determine which is smaller (step 308). The “best” version of the instruction(s) is selected and returned (step 310). It will be recognized that the “best” version may in certain circumstances be different than the smallest version. For example, with the smallest version, two (2) instructions may need to be generated which alternatively could have been generated with one 32-bit instruction. By using the 32-bit instruction, the instruction count is reduced, but not the size (which would be the same). As an example, consider the following:

mov_s r0,r16 add_s r0,r0,r0 // both 16-bit instructions, can be combined into add  r0,r16,r16 // which is one 32-bit instruction that reduces the instruction //and clock count for the program

Appendix III contains exemplary code useful for providing this determination in the context of the foregoing ARCompact ISA.

Constant Pool. Additionally, the present invention advantageously allows for constant pool plus instruction size selection for PC-relative loads. Specifically, in one exemplary embodiment (FIG. 4), the code is examined to determine the number of times each constant/address is loaded into a general purpose register (step 402). Based on this count, the given constant is placed into a constant pool per step 404 (there can be several strategically placed portions of the pool within the executable). This determination of constants is done across function boundaries. By doing this, constant/address loads from several smaller functions can be aggregated or “commoned up” into a unitary constant pool location.

In one exemplary embodiment of this method, a scan of the function being compiled is performed to determine how many times the constant (e.g., 12345678) is used. Since both negative and positive displacements exist for the pc-relative load, and the negative load does not have a compressed instruction format, a determination is made as to whether the constant should be placed into a different constant pool, or address it from an existing pool. For two exemplary uses with one forward reference and one backward reference, the size would be 10 bytes:

2-bytes for constant pool load (forward reference)

4-bytes for constant pool entry

4-bytes for constant pool load (backward reference)

However, say that there were four references. If there were one forward and 3 backward references, 18 bytes of code would be generated:

2-bytes for constant pool load (forward reference)

4-bytes for constant pool entry

4-bytes for constant pool load (backward reference)

4-bytes for constant pool load (backward reference)

4-bytes for constant pool load (backward reference)

But if the constant is duplicated and placed in another constant pool after the references, the code size would be decreased by 2 bytes:

2-bytes for constant pool load (forward reference)

4-bytes for constant pool entry

2-bytes for constant pool load (forward reference)

2-bytes for constant pool load (forward reference)

2-bytes for constant pool load (forward reference)

4-bytes for constant pool entry

Additionally, by making the load operation relative to the program counter (PC), the so-called “normal” general purpose registers or GPRs (e.g., the first 32 in the ARCompact context) are not monopolized. Furthermore, this approach provides additional flexibility in that negative or positive incrementing based on the 32-bit aligned architectural PC register may be performed. Specifically, the load instruction has an implicit base register of the architectural PC register similar to the implicit base register used in a typical PC-relative branch instruction. In many constant pool implementations, a specific GPR is assigned the based of the fixed-size constant pool which reduces the number of registers available for coloring (which can create undue register pressure that results in spilling).

Appendix IV contains exemplary code useful for implementing such functionality in the context of the ARCompact processor instruction set architecture.

Compare and Branch Pair Reduction—Furthermore, the present invention advantageously reduces compare and branch pairs down to compare/jump (“cmpjmp”) or equivalent instructions, thereby economizing on the number of processor instruction cycles needed to effectuate this function. Specifically, in one exemplary embodiment, each compare instruction that sets the condition flags (which are used in only one subsequent branch instruction) is selectively combined with the branch in order to avoid the overhead of setting the condition flags. In the exemplary ARCtangent context, a normal “cmp” (compare) followed by an immediate branch has a 1-clk penalty on the use of the condition flags. The branch also must be within a certain range of the compare; i.e., there is a limited displacement on the instruction. To accomplish this combination, the compiler of the present invention determines the size of all instructions being generated and then assembled.

In one exemplary embodiment (FIG. 5) of the method 500, a ‘cmp’ instruction followed by a pc-relative branch instruction is located (step 502). Once it is determined that it comprises a matching pair (step 504), the label associated with the branch instruction is evaluated (lookup) to determine if the difference between the branch instruction and the label (compensating for the removal of the ‘cmp’ instruction if the branch is backwards) will fit within the limited displacement of the cmpjmp instruction (step 506). If it does fit, the ‘cmp’ instruction is generally eliminated (step 508), the branch instruction is rewritten to a cmpjmp instruction (step 510), and the delay-slot of the branch (if present) is removed per step 512 (the instruction is removed before the cmpjmp instruction).

In general, the ‘cmp’ can be eliminated, but there are various compiler optimizations that allow the condition codes of the ‘cmp’ to be alive across several basic blocks in the control flow graph. When the condition codes need to be set, the first cmp/branch set is converted into a cmpjmp, and the cmp instruction re-inserted after the newly created cmpjmp instruction. By doing this, further “commoning up” of another set may be possible. For example, the following pseudo code:

CMP  status32 <- r1,r2 CJMP.eq status32,node 2,node 4 CJMP.gt status32,node 3,node 5 Would be changed to:

CMP  status32 <- r1,r2 CJMP.eq   status32,node 2,node 4 CMP  status32 <- r1,r2   // added CMP to allow for further optimizations CJMP.gt   status32,node 3,node 5 Which would then collapse into the following:

CMPJMP.eq  r1,r2,node 2,node 4 CMPJMP.gt  r1,r2,node 3,node 5

Appendix V contains exemplary code, adapted for the ARCompact environment, which accomplishes the foregoing functionality.

It will be recognized that in the context of the exemplary ARCompact ISA (and any other comparable architectures), there may a large variety of different instruction formats (e.g., an exemplary “add” instruction has up to 26 different encodings for the 32- and 16-bit formats). The ARCompact ISA is unique from the standpoint that it generates code for a homogeneous; e.g., 32-bit, instruction set initially, and then reduces the size of the instructions where applicable. Unlike prior art approaches (such as those employed by ARM, MIPS, and others), the ARCompact ISA can freely intermix 32-bit and 16-bit instructions within the same function; separate code for 32-bit and 16-bit functions need not be generated. Specifically, in one exemplary embodiment, the aforementioned initial 32-bit coding is subsequently evaluated and adapted so as to reduce code size (and to fit the 32-bit codings into the ARCtangent instruction set). The instructions are then sized and reduced to 16-bit where applicable.

Register Allocation—A significant aspect of instruction selection relates to determining which general purpose machine registers (GPRs) are used in the instructions. Under the exemplary compressed instruction stream of the ARCtangent A5 processor, for example, eight (8) GPRs may be used in most of the 16-bit instructions. Global register allocation must therefore be considered in this regard, especially with respect to coloring and spilling inadequacies. Accordingly, another aspect of the present invention provides for an improved methodology for register allocation using a limited number of registers. As shown in the exemplary embodiment of FIG. 6, the method 600 generally comprises first attempt to color the graph with a predetermined or limited number n of registers (e.g., 8) per step 602. If spilling is required (i.e., more than n−1 or 7 registers alive in any one basic block) per the determination of step 604, then the chosen registers are reassigned to the remaining GPRs per step 606. Copies are also inserted into the graph between these two “banks” (colors) of registers per step 608. Specifically, in the present embodiment, the copies are forced into the different register banks so that normal coalescing of registers within the coloring algorithms cannot occur (which would increase the size of the generated code significantly).

Next, after spilling has occurred, spills are “cleaned up” through aggressive coalescing of instructions; i.e., eliminating registers alive across an instruction.

In the illustrated embodiment, this methodology is accomplished specifically as follows. After assigning a different color to the virtual registers that are going to be spilled, a pass of local common sub-expression elimination (on a per basic block basis) is performed to remove redundant copy instructions inserted into the graph. Since the colors of the registers in the COPY instruction are different, the COPY effectively becomes a transfer instruction between banks (XFER). Next, it is determined whether the graph is colorable. If not, the “normal” spill to memory operations are performed. Once all the virtual registers have been spilled to either a register of a different color or to memory, normal register allocation is performed. Since the XFER instructions have been inserted within the graph, the coloring algorithm cannot consider the registers to be “buddies” of each other since they have distinct colors. Hence, a priority is in effect forced onto the register used within the instruction that allows use of the 8 registers that the compressed instructions require. As will be recognized, this technique can potentially cause code “bloat” since there can be many XFER instructions between the banks.

After register allocation is complete, the flow graph is analyzed and aggressive reduction of the instructions performed as previously described herein (Instruction Selection). An example of this methodology is as follows:

ADD r0,r1,r2 MOV r16,r0; spill due to register pressure on original 8 registers ADD r0,r2,r3 MOV r2,r16; re-load of spill ADD r0,r0,r2 Since the coloring algorithm tried to weigh the coloring to the reduced number of registers, the MOV instructions were generated. If no change was made to the instruction, the generated code size would be 10 bytes. If there are no other uses of the destination registers in the MOV instructions (in the above example both MOVs are superfluous), the number of instructions, as well as the clk-cnt necessary for executing the instructions, can be reduced by coalescing the MOV instructions into their surrounding def/use. In one exemplary approach, the first two instructions are coalesced by replacing the destination of the first ADD with the destination of the first MOV; the third ADD is coalesced by replacing its second source register with the source of the previous MOV instruction. After this process is complete, the following result is obtained:

ADD  r16,r1,r2; 4-bytes in size now instead of 2 ADD  r0,r2,r3; unchanged, still 2-bytes ADD  r0,r0,r16; unchanged in size, still 2bytes since we have ; an ADD encoding that allows addition of a ; compressed and a non-compressed register together ; with the destination being the same compressed register as the source By aggressively coalescing the instructions, the clock count is reduced by 1, and the code size reduced by 2 bytes. By using this technique across the entire flow graph, when spills are required, significant reduction of the code size as well as the clock counts is obtained. This is especially true since memory operations, which are typically slower then the speed of the processor, are advantageously not used. This approach has significant advantages in programs with fairly large and complex functions.

Appendix VI hereto provides exemplary code implementing the foregoing register allocation functionality in the context of the ARCtangent A5 processor.

Constant Generation—In yet another aspect of the invention, improved methods for constant generation are disclosed. Specifically, since the ARC ISA has several instructions for scaled multiply and add/sub instructions (a=b+(c*8) can be encoded in 1 instruction), a great amount of strength reduction can be performed when constant multiply operations present in the code are found. In practice, many compilers take advantage of the well known algorithm described by Robert D. Grappel in Dr. Dobb's Journal, March 1987 (or some variant thereof). This algorithm converts a multiply operation to a series of shift and add/sub instructions. For example, a multiply by the constant 9 would generate the following pseudo code:

SLL r100 <- r2,3 ADD r101 <- r100,r2 More complicated shift/add sequences generally cannot take advantage of the available instructions within the ISA. It may be desirable to generate:

MPYADD  r101 <- r100,r2,3 which could then be transformed into one 16-bit instruction versus two 16-bit instructions. Since the use of these MPYADD and MPYSUB instructions require such a different view of the constants being used, significant modifications to the typical “powers of two” method currently used are necessitated.

Appendix VII hereto provides exemplary code implementing the foregoing constant generation functionality in the context of the ARCtangent A5 processor.

Integrated Circuit (IC) Device

Referring now to FIG. 7, one exemplary embodiment of an integrated circuit device generated from the improved instruction set selection, addressing, pooling, and compression methodologies previously described herein is disclosed. As previously described, the Assignee's ARCtangent processor core configuration with improved (ARCompact) ISA is used as the basis for the IC device; however, other arrangements and configurations may be substituted if desired.

As shown in FIG. 7, the integrated circuit device 700 is digital processor SoC device having, inter alia, a processor core 702, on-chip memory 704, and an external interface 706. The device is fabricated using the customized VHDL design obtained using the method referenced subsequently herein, which is then synthesized into a logic level representation, and then reduced to a physical device using compilation, layout and fabrication techniques well known in the semiconductor arts. For example, the present invention is compatible with 0.35, 0.18, 0.13, and 0.1 micron processes, and ultimately may be applied to processes of even smaller or other resolution. An exemplary process for fabrication of the device is the 0.1 micron “Blue Logic” Cu-11 process offered by International Business Machines Corporation, although others may be used.

It will be appreciated by one skilled in the art that the IC device of FIG. 7 may also contain any commonly available peripheral such as serial communications devices, parallel ports, timers, counters, high current drivers, analog to digital (A/D) converters, digital to analog converters (D/A), interrupt processors, LCD drivers, memories and other similar devices. Further, the processor may also include other custom or application specific circuitry, such as to form a system on a chip (SoC) device useful for providing a number of different functionalities in a single package as previously referenced herein. The present invention is not limited to the type, number or complexity of peripherals and other circuitry that may be combined using the method and apparatus. Rather, any limitations are primarily imposed by the physical capacity of the extant semiconductor processes which improve over time. Therefore it is anticipated that the complexity and degree of integration possible employing the present invention will further increase as semiconductor processes improve.

It will be further recognized that any number of methodologies for synthesizing logic incorporating the enhanced ISA functionality previously discussed may be utilized in fabricating the IC device 600 of FIG. 7. One exemplary method of synthesizing integrated circuit logic having a user-customized (i.e., “soft”) instruction set is disclosed in co-pending U.S. patent application Ser. No. 09/418,663 entitled “Method And Apparatus For Managing The Configuration And Functionality Of A Semiconductor Design” filed Oct. 14, 1999, which is incorporated herein by reference in its entirety, and assigned to the Assignee hereof. Other methodologies, whether “soft” or otherwise, may be used, however.

It will be appreciated that while certain aspects of the invention have been described in terms of a specific sequence of steps of a method, these descriptions are only illustrative of the broader methods of the invention, and may be modified as required by the particular application. Certain steps may be rendered unnecessary or optional under certain circumstances. Additionally, certain steps or functionality may be added to the disclosed embodiments, or the order of performance of two or more steps permuted. All such variations are considered to be encompassed within the invention disclosed and claimed herein.

While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the art without departing from the invention. The foregoing description is of the best mode presently contemplated of carrying out the invention. This description is in no way meant to be limiting, but rather should be taken as illustrative of the general principles of the invention. The scope of the invention should be determined with reference to the claims. 

1.-23. (canceled)
 24. A method of register allocation for use in a pipelined digital processor having a mixed-length instruction set architecture, the method comprising: coloring an entity using a predetermined number of registers; evaluating whether spilling of said registers is required; if said spilling is required, then reassigning said registers to at least one remaining register; and inserting copies into the graph between said registers and said at least one remaining register. 25.-32. (canceled)
 33. A method of register allocation within a digital processor, comprising: providing a plurality of registers including virtual registers; providing a graph; assigning a different color to at least a portion of said plurality of registers that are going to be spilled; determining whether said graph is colorable; based at least on said act of determining, selectively spilling at least a portion of said virtual registers to a register of a different color; performing a register allocation; and thereafter performing code reduction.
 34. For use in a pipelined digital processor, a method of register allocation using a graph, the method comprising: coloring an entity using a predetermined number of registers; evaluating whether spilling of said registers is required; if said spilling is required, then reassigning said registers to at least one remaining register; and inserting copies of said registers into the graph between said registers and said at least one remaining register.
 35. The method of claim 34, wherein said pipelined digital processor comprises a mixed-length instruction set architecture.
 36. The method of claim 35, wherein said mixed-length instruction set architecture comprises instructions having a 16-bit length and instructions having a 32-bit length.
 37. The method of claim 34, further comprising, if said spilling is required, cleaning up one or more spills via coalescing of instructions.
 38. The method of claim 37, further comprising: assigning a different color to each register that is going to be spilled; and performing a common sub-expression elimination process.
 39. A method of register allocation within a digital processor design, comprising: providing a plurality of registers including virtual registers; providing a graph; assigning a different color to at least a portion of said plurality of registers that are going to be spilled; determining whether said graph is colorable; based at least on said act of determining, selectively spilling at least a portion of said virtual registers to a register of a different color; performing a register allocation; and thereafter performing code reduction.
 40. The method of claim 39, wherein said digital processor design comprises a mixed-length instruction set architecture.
 41. The method of claim 40, wherein said act of performing code reduction, further comprises: providing first and second versions of a plurality of instructions; and determining the more optimal of said first and second versions for at least a portion of said plurality of instructions.
 42. The method of claim 40, wherein said mixed-length instruction set architecture comprises instructions having 16-bits and instructions having 32-bits.
 43. The method of claim 40, wherein said digital processor design comprises a user-configured and extended reduced instruction set (RISC) design.
 44. A method of register allocation for use in a pipelined digital processor having a mixed-length instruction set architecture, the method comprising: coloring a graph using a predetermined number of registers, said act of coloring resulting in spilling; reassigning said registers to at least one remaining general purpose register; and inserting copies into the graph between said registers and said at least one remaining general purpose register.
 45. The method of claim 44, further comprising: cleaning spills after spilling has occurred, said act of cleaning comprising coalescing a plurality of instructions.
 46. The method of claim 44, further comprising: assigning a different color to each register that is going to be spilled; and performing a local common sub-expression elimination.
 47. The method of claim 44, wherein said mixed-length instruction set architecture comprises 16-bit and 32-bit instructions.
 48. For use with a digital processor design, a method of register allocation optimized for a mixed-length instruction set architecture (ISA), said ISA comprising instructions of a first length and instructions of a second length, said first length being less than said second length, said method comprising: providing a plurality of first registers associated with said processor design; identifying a subset of said plurality of first registers, only said subset of said plurality of first registers being available for use by the instructions of said first length; and assigning a priority to said subset of the first registers.
 49. The method of claim 48, wherein said subset of said first registers are the same color as those of said plurality of said first registers that are not part of said subset.
 50. The method of claim 48, wherein said act of assigning is not performed in cases where a register is assigned specifically to one of said first registers of a certain color by another optimization process.
 51. The method of claim 48, further comprising selecting a specific color for at least one said first registers based at least in part on at least one of: (i) compressing the size of an instruction, or (ii) reducing the overall size of a compiled function.
 52. A method of register allocation within a digital processor design comprising a mixed-length instruction set architecture, comprising: providing a plurality of registers including virtual registers; assigning a different color to at least a portion of said plurality of registers that are going to be spilled; selectively spilling at least a portion of said virtual registers to a register of a different color; performing a register allocation; and thereafter performing code reduction.
 53. The method of claim 52, wherein said mixed-length instruction set architecture comprises at least a 16-bit instruction and a 32-bit instruction.
 54. The method of claim 52, wherein said act of performing code reduction, further comprises: reading a plurality of first versions of corresponding instructions; translating each of said plurality of first versions of said instructions into a second version; and for at least a portion of said plurality of instructions, choosing the smaller of said first or second versions.
 55. The method of claim 54, wherein said digital processor design comprises a hardware description language (HDL) model, said model being generated based on user-customized inputs to a software-based design environment.
 56. The method of claim 55, wherein said method of register allocation is performed within said design environment. 